From Signal Return to Filter Capacitors: Golden Rules of PCB Anti-Interference Design! Differential-Mode Current and Common-Mode Current

From Signal Return to Filter Capacitors: Golden Rules of PCB Anti-Interference Design! Differential-Mode Current and Common-Mode Current

Radiation generation: Current causes radiation, not voltage. Static charge generates an electrostatic field; constant current produces a magnetic field; time-varying current produces both electric and magnetic fields. In any circuit, there are common-mode currents and differential-mode currents. Differential-mode signals carry data or useful signals; common-mode signals are negative effects of differential-mode operation.

Differential-mode current: Same magnitude, opposite direction (phase). Due to distributed capacitance and inductance of traces, signal-trace impedance discontinuities, and unexpected signal return paths, differential-mode current can be converted into common-mode current.

Common-mode current: Magnitude may not be equal; direction (phase) is the same.

Most external interference from a device is mainly common-mode. Differential-mode interference also exists, but common-mode interference is often several orders of magnitude stronger. External interference is also mostly common-mode. Common-mode interference itself generally does not harm equipment, but if common-mode interference converts into differential-mode interference, it becomes serious, because useful signals are all differential-mode signals.

The magnetic field of differential-mode current is mainly concentrated within the loop area formed by the differential-mode current, and outside the loop area, the magnetic flux lines cancel each other. The magnetic field of common-mode current appears outside the loop area, and the magnetic field directions produced by common-mode currents are the same. Many PCB EMC designs follow these principles.

Ways to suppress interference on a PCB include:

• Reducing differential-mode signal loop area

• Reducing high-frequency noise return (filtering, isolation, and matching)

• Reducing common-mode voltage (ground design)

Summary of PCB Design Principles

Principle 1: When the PCB clock frequency exceeds 5 MHz or signal rise time is less than 5 ns, multilayer board design is typically required.

Reason: Multilayer design provides good control of signal loop area.

Principle 2: For multilayer boards, key routing layers (clock lines, buses, interface signals, RF lines, reset lines, chip-select lines, and other control signals) should be adjacent to a solid ground plane, preferably between two ground planes.

Reason: Key signal lines are strong radiation sources or extremely sensitive; routing close to a ground plane reduces loop area, reducing radiation or improving immunity.

Principle 3: For single-layer boards, key signal traces should have ground shielding on both sides.

Reason: Ground on both sides reduces loop area and prevents crosstalk between signal lines.

Principle 4: For double-layer boards, ensure large-area ground fill in the projection plane of key signal traces, or use ground shielding and vias similar to single-layer boards.

Reason: Same effect as key signals being close to a ground plane on multilayer boards.

Principle 5: In multilayer boards, the power plane should be shrunk inward by 5H–20H relative to its adjacent ground plane (H is the distance between power and ground planes).

Reason: Shrinking the power plane reduces edge-radiation issues.

Principle 6: Routing layer projection should remain within the region of its return path plane.

Reason: If a routing layer extends outside the projection of the return plane, edge radiation increases and signal loop area enlarges, increasing differential-mode radiation.

Principle 7: In multilayer boards, avoid signals >50 MHz on TOP or BOTTOM layers.

Reason: High-frequency signals should preferably run between two plane layers to suppress radiation.

Principle 8: For boards operating above 50 MHz, if the second and second-to-last layers are routing layers, TOP and BOTTOM layers should be covered with ground copper.

Reason: High-frequency signals should be routed between two plane layers to suppress space radiation.

Principle 9: The main working power plane of the board should be adjacent to its ground plane.

Reason: Power and ground planes close together reduce power loop area.

Principle 10–11: In single- or double-layer boards, power traces must have adjacent, parallel ground traces.

Reason: Reduces power current loop area.

Principle 12: Avoid adjacent routing layers in stack-up. If unavoidable, increase spacing between routing layers and reduce spacing between a routing layer and its return plane.

Reason: Parallel traces on adjacent routing layers cause crosstalk.

Principle 13: Avoid overlapping projection areas of adjacent planes.

Reason: Overlap increases capacitive coupling between planes, causing noise transfer.

Principle 14: PCB layout should follow linear placement along the signal flow direction.

Reason: Prevents direct coupling and improves signal integrity.

Principle 15: When multiple circuit modules are on the same PCB, digital, analog, high-speed, and low-speed circuits should be separated.

Reason: Prevents mutual interference between circuit types.

Principle 16: When high-, medium-, and low-speed circuits coexist, high- and medium-speed circuits should stay away from interfaces.

Reason: Prevents high-frequency noise from radiating out through interfaces.

Principle 17: For circuits/devices with large current change (power module I/O, fans, relays), place bulk capacitors and high-frequency filter capacitors nearby.

Reason: Bulk capacitors reduce large-current loop area.

Principle 18: Power-input filter circuits should be placed near the connector.

Reason: Prevents filtered lines from being re-coupled.

Principle 19: Filter, protection, and isolation components for interface circuits should be placed near the interface.

Reason: Ensures effective protection, filtering, and isolation.

Principle 20: If both filtering and protection exist at an interface, protection must come first.

Reason: Protection handles over-voltage/current; otherwise, the filter components may be damaged.

Principle 21: Avoid coupling between input and output traces of filters, isolation, and protection circuits.

Reason: Coupling weakens their effectiveness.

Principle 22: If a “clean ground” is used at an interface, filtering and isolation components should be placed in the isolation band between clean ground and working ground.

Reason: Prevent plane coupling that weakens filtering/isolation.

Principle 23: Only filtering and protection components may be placed on “clean ground.”

Reason: Clean ground is sensitive to interference; unrelated circuits should not be placed there.

Principle 24: Strong radiation devices (crystal oscillators, relays, switching power supplies) should be at least 1000 mil away from board edges and connectors.

Reason: Prevents direct radiation or cable-coupled radiation.

Principle 25: Sensitive circuits (reset circuits, watchdogs) should be at least 1000 mil away from board edges—especially connector edges.

Reason: Connectors are susceptible to external interference such as ESD.

Principle 26: Filter capacitors for ICs should be placed as close as possible to IC power pins.

Reason: The closer the capacitor, the smaller the high-frequency loop area, reducing radiation.

Principle 27: Source-end series-termination resistors should be placed near the signal output end.

Reason: Series matching requires resistor + driver output impedance = trace characteristic impedance.

Principle 28: PCB traces should not have right angles or sharp angles.

Reason: Right-angle traces cause impedance discontinuity, ringing, overshoot, strong EMI.

Principle 29: If adjacent routing layers cannot be avoided, traces should be perpendicular, or parallel length <1000 mil.

Reason: Reduces crosstalk.

Principle 30: For internal trace layers, route clock and other key signals on inner layers.

Reason: Inner layers provide shielding.

Principle 31: Clock traces should be shielded by ground on both sides, with ground vias every 3000 mil.

Reason: Ensures equal potential along the guard trace.

Principle 32: Key signals (clock, bus, RF) must follow the 3W rule for same-layer spacing.

Reason: Reduces crosstalk.

Principle 33: For components in power paths ≥1A (fuses, beads, inductors, tantalum capacitors), pads must have at least two vias to the plane.

Reason: Reduces via impedance.

Principle 34: Differential pairs should be routed on the same layer, parallel, equal-length, with consistent impedance, and no other traces in between.

Reason: Ensures equal common-mode impedance and enhances immunity.

Principle 35: Key signals must not cross split planes (including gaps from vias or pads).

Reason: Crossing splits increases loop area.

Principle 36: If crossing split planes is unavoidable, add a bridging capacitor (1 nF) near the crossing.

Reason: Provides an intentional return path.

Principle 37: No unrelated traces should be routed beneath filters.

Reason: Stray capacitance weakens filter performance.

Principle 38: Filter input and output traces must not run parallel or cross.

Reason: Prevents direct noise coupling between pre- and post-filter lines.

Principle 39: Key signal lines must be at least 3H away from the reference plane’s edge.

Reason: Suppresses edge radiation.

Principle 40: For chassis-ground metal components, cover the projection area on the top layer with ground copper.

Reason: Distributed capacitance between enclosure and copper reduces radiation and improves immunity.

Principle 41: In single- or double-layer boards, minimize loop area during routing.

Reason: Smaller loop area = less radiation and stronger immunity.

Principle 42: When key signals change layers, place ground vias near the transition vias.

Reason: Reduces loop area.

Principle 43: Strong radiation traces (clock, bus, RF) should be kept away from external-interface signal lines.

Reason: Prevents coupling to output cables.

Principle 44: Sensitive signals (reset, chip-select, control signals) should be kept away from external-interface signals.

Reason: External lines may carry interference that could cause system malfunction.

Principle 45: For single- and double-layer boards, filter capacitors must be routed so that supply passes through the capacitor before reaching the IC.

Reason: Ensures the supply is filtered before reaching the IC and filters IC-generated noise.

Principle 46: For long power traces, place decoupling capacitors every 3000 mil (10 µF + 1000 pF).

Reason: Filters high-frequency noise on power lines.

Principle 47: Filter-capacitor traces to power and ground should be as thick and short as possible.

Reason: Lower ESL increases capacitor resonance frequency, improving high-frequency filtering.